Junjie Wu, Lian Li's Advanced Computer Architecture: 11th Conference, ACA 2016, PDF

By Junjie Wu, Lian Li

ISBN-10: 9811022089

ISBN-13: 9789811022081

ISBN-10: 9811022097

ISBN-13: 9789811022098

This booklet constitutes the refereed court cases of the eleventh Annual convention on complex computing device structure, ACA 2016, held in Weihai, China, in August 2016.

The 17 revised complete papers awarded have been rigorously reviewed and chosen from 89 submissions. The papers handle matters similar to processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and information facilities; power and reliability; intelligence computing and cellular computing.

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Extra resources for Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings

Sample text

The results are shown in Table 1 . Table 1. The parameters for multi-retention STT-RAM cells. 2 A Novel Hybrid Last Level Cache 33 From Table 1, it can be seen that the performance varies with different retention time. LRS’s access speed is even better than SRAM, while HRS’s write latency is longer than 10 ns. 2 Hybrid LLC Architecture In previous section, we get their overall performance of LRS, MRS and HRS cells. We find that LRS owns the fastest access speed, so if we adopt LRS to design LLC, the LLC’s performance can be enhanced significantly.

The blue region is STT-RAM. 1 Cache Parameters Although the long retention time of STT-RAM can offer low leakage power consumption, it leads to long write latency and high write energy. To reduce the write latency and energy, we relax the retention time of STT-RAM to improve its write performance. In Sect. 2, we find that the STT-RAM cells whose retention time are relaxed to μs and ms level can satisfy the access speed of all level caches. So we simulate the proposed HRS, MRS and LRS cells on NVSim [6] to get their parameters in 1 MB last level cache design.

Coarse Granularity Data Migration 23 We get the L2 miss trace generated by Gem5. Then the traces are fed into our Thick Cache simulator to do the performance and power estimation. 2 Baseline System The baseline system in this work is a processor core with L1 Cache and L2 Cache, without L3 Cache and a plane main memory based on DRAMSim2. The common parts of these two architectures share the same parameter of each hierarchy, except L3 Cache. The parameters of processor core and memory system are listed in Tables 1 and 2.

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Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings by Junjie Wu, Lian Li

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